GS4901B_09 Datasheet, PDF (11/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 1-1: Pin Descriptions (Continued)
Pin
Number
17
Name
VSYNC
18, 31, 38, IO_VDD
50, 62
19
FSYNC
27, 25, 24, VID_STD[5:0]
23, 22, 21
26, 44
CORE_VDD
Timing
Type Description
Non
Input
Synchronous
–
Power
Supply
Non
Input
Synchronous
Non
Input
Synchronous
–
Power
Supply
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The VSYNC external reference signal is applied to this pin by the
application layer. When the GS4901B/GS4900B is operating in
Genlock mode, the device senses the polarity of the VSYNC input
automatically, and references to the leading edge.
This signal must adhere to one of the 36 defined video standards
supported by the device. In this mode of operation, the VSYNC
input provides a vertical scanning reference signal.
The VSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer.
Section 1.4 on page 19 describes the 36 video formats recognized by
the GS4901B/GS4900B.
Most positive power supply connection for the digital I/O signals.
Connect to either +1.8V DC or +3.3V DC.
NOTE: All five IO_VDD pins must be powered by the same voltage.
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The FSYNC external reference signal is applied to this pin by the
application layer.
The first field is defined as the field in which the first broad pulse
(also known as serration) is in the first half of a line. The FSYNC
signal should be set HIGH during the first field for sync-based
references.
Then this signal must adhere to one of the 36 defined video
standards supported by the device. In this mode of operation, the
FSYNC input provides an odd/even field input reference.
The FSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer.
Section 1.4 on page 19 describes the 36 video formats recognized by
the GS4901B/GS4900B.
For blanking-based references, the FSYNC signal should be set HIGH
during the second field.
NOTE: If the input reference format does not include an F sync
signal, this pin should be held LOW.
CONTROL SIGNAL INPUTS
Signal levels are LVCMOS/LVTTL compatible.
Video Standard Select.
Used to select the desired video format for video clock and timing
signal generation.
4 different video sample clocks, as well as 9 different video format
timing signal outputs may be selected using these pins.
NOTE: The VID_STD[5:4] pins should be grounded by the application
layer since these pins are not required to select output video
standards 1 to 10.
For details on the supported video standards and video clock
frequency selection, please see Section 1.4 on page 19.
Most positive power supply connection for the digital core. Connect
to +1.8V DC.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
11 of 102