GS4901B_09 Datasheet, PDF (53/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

The PCLK1 to PCLK3 outputs may also be individually delayed with respect to the eight
TIMING_OUT signals to allow for skew control downstream from the
GS4901B/GS4900B. Using the PCLK_Phase/Divide registers, the phase of each clock
may be delayed up to a nominal 10.3ns in 16 steps of approximately 700ps each
(Table 3-6). This delay is available in addition to the genlock timing offset phase
adjustment described in Section 3.2.1 on page 35.
Table 3-6: Video Clock Phase Adjustment Host Settings
PCLKn_Phase[3:0] Setting
0 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh
h
Phase Increment (ns)
0 0.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 6.3 7.0 7.7 8.4 9.1 9.8 10.3
NOTES:
1. The phase increments listed above are nominal values.
2. The phase of PCLK is delayed relative to the TIMING_OUT pins.
Additionally, the current drive capability of PCLK1 and PCLK2 may be set high or low
using the PCLK_Phase/Divide registers. By default the current drive will be low.
3.7.2 Audio Clock Synthesis (GS4901B only)
The audio clock generator is referenced to the internal PCLK signal and is responsible for
generating the ACLK output signals. Three audio clock output pins, ACLK1 to ACLK3,
are available to the application layer.
The fundamental sampling frequency, fs, is selected using the ASR_SEL[2:0] pins as
shown in Table 3-7.
If desired, the external ASR_SEL[2:0] pins may be ignored by setting bit 2 of the
Audio_Control register and the sampling frequency may instead be programmed in the
ASR_SEL[2:0] register of the host interface (see Section 3.10.3 on page 67). Although the
external ASR_SEL[2:0] pins will be ignored, they should not be left floating.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
53 of 102