GS4901B_09 Datasheet, PDF (50/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

3.6.2.2 Loop Bandwidth of the Audio PLL (GS4901B only)
The capacitive component of the filter controlling the audio loop bandwidth is
determined by the Audio_Cap_Genlock register and the resistive component is
determined by the Audio_Res_Genlock register. These two registers are located at
addresses 39h and 3Ah, respectively, of the host interface.
To determine the setting of Audio_Res_Genlock and Audio_Cap_Genlock, the following
equations must be solved:
Audio_Res_G enlock = 47 + log₂(6 × BW × JITTERIN × A _Feedback_D ivide )
Audio_Cap_G enlock ≤ Audio_Res_G enlock– 21
where:
BW = the desired audio PLL loop bandwidth
JITTERIN = Jitter present on output PCLK, in seconds.
A_Feedback_Divide = the numerator of the audio PLL divide ratio
A_Feedback_Divide is defined by the following equation:
A_Feedback_D ivide
A^{-----_---R----e---f-e---r--e---n---c---e--_---D-----i-v---i--d---e-}
=
n × _f---_o-^f--^su----_t
Where f_s is the fundamental audio sampling frequency and f_out is the output video clock
frequency. The integer constant, n, will depend on the fundamental audio sampling
frequency as shown in Table 3-5.
Table 3-5: Integer Constant Value
ASR_SEL[2:0]=100b
Enable_384fs = 0
Value of constant (n)
NO
X
3072
YES
YES
1024
YES
NO
1536
NOTES:
1. Enable_384fs corresponds to bit 5 of address 31h of the host interface. It is LOW by default.
2. ‘X’ signifies ‘don’t care.’ This bit will be ignored when determining n.
NOTE: The value programmed in the Audio_Res_Genlock register must be between 32
and 42. The value programmed in the Audio_Cap_Genlock register must be greater than
10. These limits define the exact range of loop bandwidth adjustment available.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
50 of 102