GS4901B_09 Datasheet, PDF(67/102 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B_09 Datasheet, PDF (67/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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Table 3-13: Configuration and Status Registers

RSVD

H_Period

H_16_Period

V_Lines

V_2_Lines

F_Lines

Address

00h - 09h

0Ah

0Bh

0Ch

0Dh

0Eh

Bit

15-0

Description

R/W

Reserved.

Contains the number of 27MHz pulses in the input R

H Sync period. This register is set by the Reference

Format Detector block using the H Sync signal

present on the external HSYNC input pin.

NOTE: If the reference is removed this register will

remain unchanged until a new reference with a

different HSYNC period is applied.

Reference: Section 3.5.1 on page 43

Contains the number of 27MHz pulses in 16 H Sync R

periods. This register is set by the Reference Format

Detector block using the H Sync signal present on

the external HSYNC input pin. It is useful for 1/1.001

data detection.

NOTE: If the reference is removed this register will

remain unchanged until a new reference with a

different HSYNC period is applied.

Reference: Section 3.5.1 on page 43

Contains the number of H Sync periods in the input R

V Sync interval. This register is set by the Reference

Format Detector block using the signals present on

the external HSYNC and VSYNC input pins.

NOTE: If the reference is removed this register will

remain unchanged until a new reference with a

different VSYNC period is applied.

Reference: Section 3.5.1 on page 43

Contains the number of H Sync periods in 2 V Sync R

intervals. This register is set by the Reference

Format Detector block using the signals present on

the external HSYNC and VSYNC input pins.

NOTE: If the reference is removed this register will

remain unchanged until a new reference with a

different VSYNC period is applied.

Reference: Section 3.5.1 on page 43

Contains the number of H Sync periods in the input R

F Sync interval. This register is set by the Reference

Format Detector block using the signals present on

the external HSYNC and FSYNC input pins.

NOTE: If the reference is removed this register will

remain unchanged until a new reference is applied.

If the new reference does not include an FSYNC

pulse, this register will be set to zero.

Reference: Section 3.5.1 on page 43

Default

N/A

GS4901B/GS4900B SD Clock and Timing Generator

with GENLOCK

Data Sheet

37703 - 4

December 2009

67 of 102

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