GS4901B_09 Datasheet, PDF (13/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 1-1: Pin Descriptions (Continued)
Pin
Number
36
Name
TIMING_OUT_2
37
TIMING_OUT_3
39
TIMING_OUT_4
Timing
Type Description
Synchronous
with PCLK1
~ PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio
timing (GS4901B only); USER_1~4.
See Section 1.5 on page 23 for signal descriptions.
NOTE: Default output is H blanking.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current
drive will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Synchronous
with PCLK1
~ PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio
timing (GS4901B only); USER_1~4.
See Section 1.5 on page 23 for signal descriptions.
NOTE: Default output is V Sync.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current
drive will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Synchronous
with PCLK1
~ PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio
timing (GS4901B only); USER_1~4.
See Section 1.5 on page 23 for signal descriptions.
NOTE: Default output is V blanking.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current
drive will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
13 of 102