GS4901B_09 Datasheet, PDF (31/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 2-2: AC Electrical Characteristics (Continued)
V_DD = 1.8V, T_A = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units Notes
Digital Timing Output Delay
t_OD
Time
Digital Timing Output Hold Time t_OH
Digital Timing Output Rise/Fall –
Times
15pF load
20% - 80%
–
–
–
–
–
–
1
IO_VDD = 1.8V
–
current drive = LOW
IO_VDD = 3.3V
–
current drive = LOW
IO_VDD = 1.8V
–
current drive = HIGH
IO_VDD = 3.3V
–
current drive = HIGH
–
4.3
ns
5
–
–
ns
5
–
3.0
ns
–
–
1.5
ns
–
–
2.5
ns
–
–
1.4
ns
–
GSPI
GSPI Input Clock Frequency
f_GSPI
–
–
–
10.0
MHz
6
GSPI Clock Duty Cycle
DC_GSPI
–
40
–
60
%
6
GSPI Input Setup Time
t₃ in
–
Figure 3-15
1.5
–
–
ns
6
GSPI Input Hold Time
t₈ in
–
Figure 3-15
1.5
–
–
ns
6
NOTES
1. The video output clock may be directly connected to Gennum’s GS9062 serializer for a SMPTE-compliant SDI output with output jitter below
0.2UI.
2. All output standards EXCEPT VID_STD[5:0] = 1 (450ps typ.) and VID_STD[5:0] = 5 or 6 (500ps typ.)
3. Timings from any CLK output to any other CLK output.
4. If fs=96kHz and ACLK is configured to output a clock signal at 192fs or 384fs, a 512fs clock will typically have a 33% duty cycle distortion.
See Section 3.7.2 on page 54.
5. With PCLK phasing delay set to nominal (zero offset), each increment of the clock phasing adjustment decreases output hold time and delay
time by a nominal 700ps. The times t_OD and t_OH are defined in Figure 2-1.
6. For detailed GSPI timing parameters, please refer to Table 3-12.
PCLK
tOH
tOD
50%
TIMING_OUT
VOH
VOL
VOH
VOL
Figure 2-1: PCLK to TIMING_OUT Signal Output Timing
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
31 of 102