MC908JB16DWE Datasheet, PDF (99/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
VDD
INTERNAL
PULL-UP
÷2
CLOCK
CONTROL
CLOCK GENERATORS
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
OSCDCLK (FROM OSC)
OSCOUT (FROM OSC)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
LVI RESET (FROM LVI MODULE)
USB RESET (FROM USB MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Signal Name
OSCDCLK
OSCOUT
IAB
IDB
PORRST
IRST
R/W
Figure 8-1. SIM Block Diagram
Table 8-1. SIM Module Signal Name Conventions
Description
Clock doubler output which has twice the frequency of OSC1 from the oscillator
The OSCDCLK frequency divided by two. This signal is again divided by two in the
SIM to generate the internal bus clocks.
(Bus clock = OSCDCLK ÷ 4 = OSCXCLK ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
99