MC908JB16DWE Datasheet, PDF (228/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface
12.7 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
12.8 I/O Signals
Port C shares two of its pins with the SCI module. The two SCI I/O pins
are:
• PTC0/TxD — Transmit data
• PTC1/RxD — Receive data
12.8.1 TxD (Transmit Data)
The PTC0/TxD pin is the serial data output from the SCI transmitter. The
SCI shares the PTC0/TxD pin with port C. When the SCI is enabled, the
PTC0/TxD pin is an output regardless of the state of the DDRC0 bit in
data direction register C (DDRC).
12.8.2 RxD (Receive Data)
The PTC1/RxD pin is the serial data input to the SCI receiver. The SCI
shares the PTC1/RxD pin with port C. When the SCI is enabled, the
PTC1/RxD pin is an input regardless of the state of the DDRC1 bit in
data direction register C (DDRC).
Technical Data
228
Serial Communications Interface Module (SCI)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor