MC908JB16DWE Datasheet, PDF (300/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Computer Operating Properly (COP)
17.4.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
17.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
17.4.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
CONFIG register. (See Figure 17-2.)
17.4.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the CONFIG register. (See Figure 17-2.)
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
LVIDR LVI5OR3 URSTD LVID SSREC COPRS STOP
Write:
Reset: 0*
0*
0*
0*
0
0
0
* LVIDR, LVI5OR3, URSTD, and LVID, are reset by POR or LVI reset only.
Figure 17-2. Configuration Register (CONFIG)
Bit 0
COPD
0
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is 2¹³ – 2⁴ OSCDCLK cycles
0 = COP timeout period is 2¹⁸ – 2⁴ OSCDCLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
Technical Data
300
Computer Operating Properly (COP)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor