MC908JB16DWE Datasheet, PDF (103/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
8.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 OSCDCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. (See Figure
8-5.) An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, the USB module or POR. (See Figure 8-6 .
Sources of Internal Reset.)
NOTE:
For LVI or POR resets, the SIM cycles through 4096 OSCDCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST shown in
Figure 8-5.
IRST
RST
OSCDCLK
IAB
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 8-5. Internal Reset Timing
VECTOR HIGH
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
USB
INTERNAL RESET
Figure 8-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
103