MC908JB16DWE Datasheet, PDF (305/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
18.4.2 Low V_REG Detector
The low V_REG detector circuit monitors the V_REG voltage and forces a
LVI reset when the V_REG voltage falls below the trip voltage. The V_REG
LVI circuit can be disabled by the setting the LVIDR bit in CONFIG.
NOTE: There is no LVI circuit for V_REGA.
18.5 LVI Control and Configuration
Three bits in the configuration register (CONFIG) control the operation
of the LVI module.
Address: $001F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LVIDR LVI5OR3 URSTD LVID SSREC COPRS STOP COPD
Write:
Reset: 0*
0*
0*
0*
0
0
0
0
= Unimplemented
* LVIDR, LVI5OR3, URSTD, and LVID bits are reset by POR (power-on reset) or LVI reset only.
Figure 18-2. Configuration Register (CONFIG)
LVIDR — LVI Disable Bit for V_REG
LVIDR disables the LVI circuit for V_REG.
1 = LVI circuit for V_REG disabled
0 = LVI circuit for V_REG enabled
LVI5OR3 — LVI Trip Point Voltage Select Bit for V_DD
LVI5OR3 selects the trip point voltage of the LVI circuit for V_DD. See
Section 20. Electrical Specifications for the trip voltage tolerances.
1 = LVI trips at 3.3V
0 = LVI trips at 2.4V
LVID — LVI Disable Bit for V_DD
LVID disables the LVI circuit for V_DD.
1 = LVI circuit for V_DD disabled
0 = LVI circuit for V_DD enabled
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Low-Voltage Inhibit (LVI)
Technical Data
305