MC908JB16DWE Datasheet, PDF (258/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
13.9.4 VCO Divider Select Register Low
The VCO divider select registers low (PNSL1 and PNSL2) contain the
programming information for the low byte of VCO feedback divider, N.
Address: $0054
Bit 7
6
5
4
3
2
1
Bit 0
Read:
VDS1_7 VDS1_6 VDS1_5 VDS1_4 VDS1_3 VDS1_2 VDS1_1 VDS1_0
Write:
Reset: 0
1
1
1
1
1
0
1
Figure 13-10. PLL1 N Divider Select Register Low (PNSL1)
Address: $0057
Bit 7
Read:
VDS2_7
Write:
Reset: 0
6
VDS2_6
1
5
VDS2_5
1
4
VDS2_4
1
3
VDS2_3
1
2
VDS2_2
1
1
VDS2_1
0
Bit 0
VDS2_0
1
Figure 13-11. PLL2 N Divider Select Register Low (PNSL2)
VDSx_[7:0] — VCO Divider Select Bits
These read/write bits control the low byte of the VCO feedback
divider, N.
NOTE: Writing to PNSL also latches the respective high bits, VDSx_[11:8].
Technical Data
258
Clock Generator Module (CGM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor