MC908JB16DWE Datasheet, PDF (117/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
The SIM disables the oscillator signals (OSCOUT and OSCDCLK) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096
OSCDCLK cycles down to 2048. This is ideal for applications using
canned oscillators that do not require long startup times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 8-17 shows stop mode entry timing.
NOTE: To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction
Figure 8-17. Stop Mode Entry Timing
OSCDCLK
INT/BREAK
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 8-18. Stop Mode Recovery from Interrupt or Break
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
117