MC908JB16DWE Datasheet, PDF (323/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Electrical Specifications
Characteristic⁽¹⁾
Condition
Symbol
Min
Typ⁽²⁾
Max
Unit
Output capacitive load
C_L
PLL frequency list
Rx LO 1
Rx LO 2
Rx LO 3
Rx LO 4
Rx LO 5
PLL output signal frequency
accuracy
Exclude crystal
OSC tolerance
PLL output signal phase
noise level
At ±1kHz offset
from carrier
—
—
10
pF
26.54
—
26.59
26.64
—
MHz
26.69
26.74
—
± 100
±4
—
Hz
ppm
—
– 40
—
dBc/Hz
VCO frequency range
26
—
28
MHz
PLL lock duration
Duration for Lock bit detection
channel to
channel⁽³⁾
Wait/stop mode to
active⁽⁴⁾
Within ±10% final
frequency⁽⁵⁾
—
10
—
ms
—
20
—
ms
—
10
—
ms
PLL stop duration
PLL output sideband
noise level⁽⁶⁾
PLL module from
active to disable
mode.
At offset >4kHz
At offset >42.5kHz
—
—
1
ms
—
– 40
– 50
—
dBc
PLL output channel
intermodulation products⁽⁷⁾
At offset >42.5kHz
—
– 50
—
dBc
Notes:
1. V_DDA = 4.0 to 5.5 Vdc, V_SSA = 0 Vdc, T_A = T_L to T_H, with the pre-defined programming setting for the PLL
(see 13.10 Pre-Defined VCO Output Frequency Settings) and under steady state condition, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Defined as the total time for PLL module switching from channel-to-channel and the frequency is stable with ±60ppm. The
reference frequency should be greater than 32kHz.
4. Defined as the total time for PLL module active from wait/stop mode to the frequency is stable with ±60ppm error. The
reference frequency should be greater than 32kHz.
5. Defined as the total time for PLL Lock bit setup from un-lock to lock state with the frequency is stable with ±10% error. The
reference frequency should be greater than 32kHz.
6. Side-band component generate from reference frequency modulation on carrier.
7. Noise component generate from adjacent channel carrier when both PLLs are enable.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Electrical Specifications
Technical Data
323