MC908JB16DWE Datasheet, PDF (255/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
13.8 Programming the PLL
With the PLLs off (PLLON = 0), use the following procedure to initialize
both PLLs:
1. Write $80 to the VCO control register (PVCR).
2. Write $70 to the phase detector register (PDCR).
Then for each PLL, use the following procedure to program the VCO and
reference dividers:
3. Write data to the VCO and reference divider select register high
(PNRH).
4. Write data to the VCO divider select register low (PNSL).
5. Write data to the reference divider select register low (PRSL).
6. Set PLLON = 1 in the bandwidth control register to enable the PLL.
To reprogram the PLL frequency, clear the PLLON bit (PLLON =0) and
repeat steps 3 to 6.
NOTE: Do not program both PLLs to the same frequency. A difference of 50kHz
or more is recommended between the two PLL outputs.
13.9 CGM I/O Registers
These registers control and monitor operation of the CGMs:
• Bandwidth control register (PBWC)
• VCO control register (PVCR)
• PLL1 VCO and reference divider select register high (PNRH1)
• PLL1 VCO divider select register low (PNSL1)
• PLL1 reference divider select register low (PRSL1)
• PLL2 VCO and reference divider select register high (PNRH2)
• PLL2 VCO divider select register low (PNSL2)
• PLL2 reference divider select register low (PRSL2)
• Phase detector control register (PDCR)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
255