MC908JB16DWE Datasheet, PDF (299/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Computer Operating Properly (COP)
A COP reset pulls the RST pin low for 32 OSCDCLK cycles and sets the
COP bit in the SIM reset status register (SRSR).
NOTE:
In monitor mode, the COP is disabled if the RST pin or the IRQ is held
at V_TST. During the break state, V_TST on the RST pin disables the COP.
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
17.4 I/O Signals
The following paragraphs describe the signals shown in Figure 17-1.
17.4.1 OSCDCLK
OSCDCLK is the crystal oscillator clock doubler output signal. Its
frequency is two times the crystal frequency.
17.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
17.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 17.5 COP
Control Register) clears the COP counter and clears bits 12 through 5
of the prescaler. Reading the COP control register returns the low byte
of the reset vector.
17.4.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096
OSCDCLK cycles after power-up.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Computer Operating Properly (COP)
Technical Data
299