MC908JB16DWE Datasheet, PDF (260/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
13.9.6 Phase Detector Control Register (PDCR)
The phase detector control register configures the phase detector for
both PLLs.
Address: $0059
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PHD_7
Write:
PHD_6
PHD_5
PHD_4
PHD_3
PHD_2
PHD_1
PHD_0
Reset: 1
0
0
1
0
0
0
0
Figure 13-14. Phase Detector Control Register (PDCR)
PHD_[7:0] — Phase detector Control Bits for both PLLs
Set PHD_[7:0] = $70 for maximum performance.
13.10 Pre-Defined VCO Output Frequency Settings
The exact frequency values for the following required channels cannot
be synthesized by using a reference frequency higher than 10kHz. An
absolute offset frequency from +1.66kHz to +1.89kHz will be introduced
for different channels and the maximum relative offset is only ±115Hz
with 1.775kHz as the center point (see Table 13-1 . Predefined
Programming Setting for PLL). The absolute offset frequency can be
further minimized by reducing the crystal frequency by 60 ppm (360Hz)
in actual application.
Channel
Frequency
(MHz)
26.54
26.59
26.64
26.69
26.74
Table 13-1. Predefined Programming Setting for PLL
Crystal
Frequency
(MHz)
12
12
12
12
12
Divider R
288
338
268
370
302
Reference
Frequency
(kHz)
41.67
35.50
44.78
32.43
39.74
Divider N
637
749
595
823
673
VCO
Frequency
(MHz)
26.54166
26.59171
26.64179
26.69189
26.74172
Absolute
Offset
(kHz)
+1.66
+1.71
+1.79
+1.89
+1.72
Technical Data
260
Clock Generator Module (CGM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor