MC908JB16DWE Datasheet, PDF (157/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading TIM channel x status and control register with CHxF
set and then writing a logic 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing logic 0
to CHxF has no effect. Therefore, an interrupt request cannot be lost
due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
CH01IE — CH0F and CH1F Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests when
CH0F and CH1F are set.
Reset clears the CH01IE bit.
1 = CPU interrupt requests when CH0F and CH1F are set
0 = No CPU interrupt requests when CH0F and CH1F are set
MS0B — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MS0B exists only in the TIM1 channel 0 and TIM2 channel 0 status
and control registers.
Setting MS0B disables the channel 1 status and control register.
Reset clears the MS0B bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input
capture operation or unbuffered output compare/PWM operation.
See Table 10-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Timer Interface Module (TIM)
Technical Data
157