MC908JB16DWE Datasheet, PDF (257/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
13.9.3 VCO and Reference Divider Select Registers High
The VCO and reference divider select registers high (PNRH1 and
PNRH2) contain the programming information for the high byte of VCO
feedback divider, N, and reference divider, R.
Address: $0053
Bit 7
6
5
4
3
Read:
0
VDS1_11 VDS1_10 VDS1_9 VDS1_8
Write:
Reset: 0
0
1
0
0
= Unimplemented
2
1
Bit 0
0
RDS1_9 RDS1_8
0
0
0
Figure 13-8. PLL1 N & R Divider Select Register High (PNRH1)
Address: $0056
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
VDS2_11 VDS2_10 VDS2_9 VDS2_8
Write:
0
RDS2_9 RDS2_8
Reset: 0
0
1
0
0
0
0
0
= Unimplemented
Figure 13-9. PLL2 N & R Divider Select Register High (PNRH2)
VDSx_[11:8] — VCO Divider Select Bits
These read/write bits control the high byte of the VCO feedback
divider, N.
RDSx_[9:8] — Reference Divider Select Bits
These read/write bits control the high byte of the reference divider, R.
NOTE: The VDSx_[11:8] and RDSx_[9:8] bits are not latched until the
respective low bytes are written.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
257