MC908JB16DWE Datasheet, PDF (248/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
13.10 Pre-Defined VCO Output Frequency Settings . . . . . . . . . . . . 260
13.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
13.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
13.2 Introduction
This section describes the clock generation module (CGM). The CGM
operates at the frequency of the crystal, OSCXCLK, and generates
frequencies in the 27MHz range. This frequency range is targeted for RF
applications, such as in a local oscillator in a down conversion mixer
receiver.
This particular MCU has two clock generation modules which are
denoted as CGM1 and CGM2. Each CGM contains all the functional
blocks for PLL control of a VCO.
NOTE:
References to either CGM1 or CGM2 may be made in the following text
by omitting the CGM number. For example, CGMOUT may refer
generically to CGMOUT1 and CGMOUT2, and LOCK bit may refer to
LOCK1 and LOCK2 bits.
Addr.
Register Name
Bit 7
6
5
PLL Bandwidth Control ^Read:
R
LOCK1
R
$0051
Register Write:
(PBWC) _Reset:
0
$0052
Read:
VCO Control Register
(PVCR)
Write:
Reset:
VCO_7
0
VCO_6
0
VCO_5
1
PLL1 N & R Divider Select ^Read: _{VDS1_11 VDS1_10}
$0053
Register High Write:
(PNRH1) _Reset:
0
0
VDS1_9
1
4
PLLON1
0
VCO_4
1
VDS1_8
0
3
R
VCO_3
0
0
0
2
LOCK2
0
VCO_2
0
0
0
1
Bit 0
R PLLON2
0
VCO_1 VCO_0
0
0
RDS1_9 RDS1_8
0
0
Figure 13-1. CGM I/O Register Summary
Technical Data
248
Clock Generator Module (CGM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor