MC908JB16DWE Datasheet, PDF (102/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 8.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). (See 8.8 SIM Registers.)
8.4.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 OSCDCLK cycles, assuming that neither the POR nor
the LVI was the source of the reset. See Table 8-2 for details.
Figure 8-4 shows the relative timing.
Table 8-2. PIN Bit Set Timing
Reset Type
POR/LVI
All others
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
OSCOUT
RST
IAB PC
VECT H VECT L
Figure 8-4. External Reset Timing
Technical Data
102
System Integration Module (SIM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor