MC908JB16DWE Datasheet, PDF (100/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
Addr.
Register Name
Bit 7
6
5
4
3
Read:
$FE00
SIM
Break
Status
Register
(SBSR)
Write:
R
R
R
R
R
Reset:
Note: Writing a logic 0 clears SBSW.
Read: POR
PIN
COP
ILOP
ILAD
$FE01
SIM
Reset
Status
Register
(SRSR)
Write:
POR: 1
0
0
0
0
SIM Break Flag Control ^Read: _BCFE
R
R
R
R
$FE03
Register Write:
(SBFCR) _{Reset: 0}
Read: IF6
IF5
IF4
IF3
IF2
$FE04
Interrupt Status Register 1
(INT1)
Write:
R
R
R
R
R
Reset: 0
0
0
0
0
Read: IF14
IF13
IF12
IF11
IF10
$FE05
Interrupt Status Register 2
(INT2)
Write:
R
R
R
R
R
Reset: 0
0
0
0
0
Figure 8-2. SIM I/O Register Summary
2
1
Bit 0
SBSW
R
R
See note
0
USB
LVI
0
0
0
0
R
R
R
IF1
0
0
R
R
R
0
0
0
IF9
IF8
IF7
R
R
R
0
0
0
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 8-3.
FROM OSC
OSCDCLK
OSCOUT
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 8-3. SIM Clock Signals
Technical Data
100
System Integration Module (SIM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor