MC908JB16DWE Datasheet, PDF (249/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
$0054
PLL1 N Divider Select ^Read:
Register Low Write:
(PNSL1) _Reset:
VDS1_7
0
VDS1_6
1
VDS1_5
1
VDS1_4
1
VDS1_3
1
VDS1_2
1
VDS1_1
0
VDS1_0
1
$0055
PLL1 R Divider Select ^Read: _{RDS1_7}
Register Low Write:
(PRSL1) _Reset:
1
RDS1_6
0
RDS1_5
0
RDS1_4
1
RDS1_3
0
RDS1_2
0
RDS1_1
0
RDS1_0
0
PLL2 N & R Divider Select ^Read: _{VDS2_11 VDS2_10 VDS2_9 VDS2_8}
0
$0056
Register High Write:
(PNRH2) _Reset:
0
0
1
0
0
0
RDS2_9 RDS2_8
0
0
0
$0057
PLL2 N Divider Select ^Read:
Register Low Write:
(PNSL1) _Reset:
VDS2_7
0
VDS2_6
1
VDS2_5
1
VDS2_4
1
VDS2_3
1
VDS2_2
1
VDS2_1
0
VDS2_0
1
$0058
PLL2 R Divider Select ^Read: _{RDS2_7}
Register Low Write:
(PRSL2) _Reset:
1
RDS2_6
0
RDS2_5
0
RDS2_4
1
RDS2_3
0
RDS2_2
0
RDS2_1
0
RDS2_0
0
$0059
Phase Detector Control ^Read:
Register Write:
(PDCR) _Reset:
PHD_7
1
PHD_6
0
PHD_5
0
PHD_4
1
PHD_3
0
PHD_2
0
PHD_1
0
PHD_0
0
Figure 13-1. CGM I/O Register Summary
13.3 Functional Description
Figure 13-2 shows the structure of one CGM. There are two CGMs in
this MCU.
The two CGMs are independently programmable, with their respective
outputs at the CGMOUT1 and CGMOUT2 pins.
The following paragraphs describes the CGM circuit blocks and internal
signals.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
249