MC908JB16DWE Datasheet, PDF (259/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
13.9.5 Reference Divider Select Register Low
The divider select registers low (PRSL1 and PRLS2) contain the
programming information for the low byte of reference divider, R.
Address: $0055
Bit 7
6
5
4
3
2
1
Bit 0
Read:
RDS1_7 RDS1_6 RDS1_5 RDS1_4 RDS1_3 RDS1_2 RDS1_1 RDS1_0
Write:
Reset: 1
0
0
1
0
0
0
0
Figure 13-12. PLL1 R Divider Select Register Low (PRSL1)
Address: $0058
Bit 7
Read:
RDS2_7
Write:
Reset: 1
6
RDS2_6
0
5
RDS2_5
0
4
RDS2_4
1
3
RDS2_3
0
2
RDS2_2
0
1
RDS2_1
0
Bit 0
RDS2_0
0
Figure 13-13. PLL2 R Divider Select Register Low (PRSL2)
RDSx_[7:0] — Reference Divider Select Bits
These read/write bits control the high byte of the reference divider, R.
NOTE: Writing to PRSL also latches the respective high bits, RDSx_[9:8].
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
259