MC908JB16DWE Datasheet, PDF (190/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Universal Serial Bus Module (USB)
TP0SIZ3–TP0SIZ0 — Endpoint 0 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the
next IN token request for endpoint 0. These bits are cleared by reset.
11.8.6 USB Control Register 1
Address: $003C
Bit 7
Read:
T1SEQ
Write:
Reset: 0
6
STALL1
0
5
TX1E
0
4
3
2
1
Bit 0
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
0
0
0
0
0
Figure 11-20. USB Control Register 1 (UCR1)
T1SEQ — Endpoint 1 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction directed to
endpoint 1. Toggling of this bit must be controlled by software. Reset
clears this bit.
1 = DATA1 token active for next endpoint 1 transmit
0 = DATA0 token active for next endpoint 1 transmit
STALL1 — Endpoint 1 Force Stall Bit
This read/write bit causes endpoint 1 to return a STALL handshake
when polled by either an IN or OUT token by the USB host controller.
Reset clears this bit.
1 = Send STALL handshake
0 = Default
TX1E — Endpoint 1 Transmit Enable
This read/write bit enables a transmit to occur when the USB host
controller sends an IN token to endpoint 1. The appropriate endpoint
enable bit, ENABLE1 bit in the UCR3 register, also should be set.
Software should set the TX1E bit when data is ready to be
transmitted. It must be cleared by software when no more data needs
to be transmitted.
Technical Data
190
Universal Serial Bus Module (USB)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor