MC908JB16DWE Datasheet, PDF (158/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output
level of the TCHx pin. See Table 10-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register.
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to an I/O port, and pin TCHx is available as a general-purpose I/O pin.
Table 10-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 10-3. Mode, Edge, and Level Selection
MS0B:MSxA ELSxB:ELSxA
Mode
Configuration
X0
00
Pin under port control;
initial output level high
Output preset
X1
00
Pin under port control;
initial output level low
00
01
Capture on rising edge only
00
10
Input capture ^{Capture on falling edge only}
00
11
Capture on rising or
falling edge
01
01
Output
Toggle output on compare
01
10
compare or
Clear output on compare
01
11
PWM⁽¹⁾
Set output on compare
1X
01
Buffered
Toggle output on compare
1X
10
output
compare or
Clear output on compare
1X
11
buffered PWM
Set output on compare
Notes:
1. Enable only one channel for unbuffered output compare or PWM functions. Avoid the
following configuration: MS0B = 0, MS0A = 1, MS1A = 1, and ELSxB:A ≠ 00
Technical Data
158
Timer Interface Module (TIM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor