MC908JB16DWE Datasheet, PDF (298/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Computer Operating Properly (COP)
17.3 Functional Description
Figure 17-1 shows the structure of the COP module.
OSCDCLK
12-BIT COP PRESCALER
RESET CIRCUIT
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COPEN (FROM SIM)
COP DISABLE
(COPD FROM CONFIG)
RESET
COPCTL WRITE
COP RATE SEL
(COPRS FROM CONFIG)
6-BIT COP COUNTER
CLEAR
COP COUNTER
Figure 17-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2¹⁸ – 2⁴ or 2¹³ – 2⁴
OSCDCLK cycles, depending on the state of the COP rate select bit,
COPRS, in configuration register 1. With a 2¹⁸ – 2⁴ OSCDCLK cycle
overflow option, a 24MHz OSCDCLK (12MHz crystal) gives a COP
timeout period of 10.92ms. Writing any value to location $FFFF before
an overflow occurs prevents a COP reset by clearing the COP counter
and stages 12 through 5 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
Technical Data
298
Computer Operating Properly (COP)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor