MC908JB16DWE Datasheet, PDF (160/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
Technical Data
160
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
Address: T1CH0H, $0011 and T2CH0H, $0047
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
Write:
9
Bit 8
Reset:
Indeterminate after reset
Figure 10-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0012 and T2CH0L $0048
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 10-13. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0014 and T2CH1H, $004A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
Write:
9
Bit 8
Reset:
Indeterminate after reset
Figure 10-14. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $0015 and T2CH1L, $004B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
Write:
Reset:
5
4
3
2
Indeterminate after reset
1
Bit 0
Figure 10-15. TIM Channel 1 Register Low (TCH1L)
Timer Interface Module (TIM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor