MC908JB16DWE Datasheet, PDF (256/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
13.9.1 Bandwidth Control Register
The bandwidth control register (PBWC) contains control/status bits for
both PLLs.
Address: $0051
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R
Write:
LOCK1
R
PLLON1
R
LOCK2
R
PLLON2
Reset:
0
0
0
0
= Unimplemented
R = Reserved
Figure 13-6. PLL Bandwidth Control Register (PBCR)
LOCKx — Lock Indicator Bit
This read-only bit becomes set when the VCO clock is locked (running
at the programmed frequency).
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
PLLONx — PLL On Bit
This read/write bit activates each PLL and enables the VCO clock.
1 = PLL on
0 = PLL off
13.9.2 VCO Control Register (PVCR)
The VCO control register configures the VCO for both PLLs.
Address: $0052
Bit 7
6
5
4
3
2
1
Read:
VCO_7
Write:
VCO_6
VCO_5
VCO_4
VCO_3
VCO_2
VCO_1
Reset: 0
0
1
1
0
0
0
Figure 13-7. VCO Control Register (PVCR)
Bit 0
VCO_0
0
VCO_[7:0] — VCO Control Bits for both PLLs
Set VCO_[7:0] = $80 for maximum performance.
Technical Data
256
Clock Generator Module (CGM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor