MC908JB16DWE Datasheet, PDF (301/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Computer Operating Properly (COP)
17.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clears COP counter (any value)
Reset:
Unaffected by reset
Figure 17-3. COP Control Register (COPCTL)
17.6 Interrupts
The COP does not generate CPU interrupt requests.
17.7 Monitor Mode
When monitor mode is entered with V_TST on the IRQ pin, the COP is
disabled as long as V_TST remains on the IRQ pin or the RST pin. When
monitor mode is entered by having blank reset vectors and not having
V_TST on the IRQ pin, the COP is automatically disabled until a POR
occurs.
17.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Computer Operating Properly (COP)
Technical Data
301