MC908JB16DWE Datasheet, PDF (126/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor ROM (MON)
9.4.1 Entering Monitor Mode
Table 9-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 19200 baud provided one of the following sets
of conditions is met:
1. If IRQ = V_TST:
– External clock on OSC1 is 12MHz
– PTA3 = high
– PTE3 = high
2. If $FFFE & $FFFF is blank (contains $FF):
– External clock on OSC1 is 12MHz
– IRQ = V_DD
– PTE3 = high
Table 9-1. Mode Entry Requirements and Options
External Clock,
f_XCLK
Bus
Frequency,
f_BUS
Comments
V_TST(2)
X
10011
Factory use only
12 MHz
12 MHz
(f_XCLK)
High-voltage entry to
monitor mode.
38400 baud communication
on PTA0. COP disabled.
V_TST(2)
X
11011
12 MHz
6 MHz
(f_XCLK ÷ 2)
High-voltage entry to
monitor mode.
19200 baud communication
on PTA0. COP disabled.
BLANK
V_DD
(contain 1 X X X 1
$FF)
12 MHz
6 MHz
(f_XCLK ÷ 2)
Low-voltage entry to
monitor mode.
19200 baud communication
on PTA0. COP disabled.
V_DD
NOT
BLANK
1
X
X
X
X
12 MHz
6 MHz
(f_XCLK ÷ 2)
Enters user mode.
If $FFFE and $FFFF is
blank, MCU will encounter
an illegal address reset.
Notes:
1. PTA3 = 0: Bypasses the divide-by-two prescaler to SIM when using V_TST for monitor mode entry.
2. See Section 20. Electrical Specifications for V_TST voltage level requirements.
Technical Data
126
Monitor ROM (MON)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor