MC908JB16DWE Datasheet, PDF (72/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration Register (CONFIG)
5.4 Configuration Register
Address: $001F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LVIDR LVI5OR3 URSTD LVID SSREC COPRS STOP COPD
Write:
Reset: 0*
0*
0*
0*
0
0
0
0
* LVIDR, LVI5OR3, URSTD, and LVID bits are reset by POR (power-on reset) or LVI reset only.
Figure 5-1. Configuration Register (CONFIG)
NOTE:
LVIDR — LVI Disable Bit for V_REG
LVIDR disables the LVI circuit for V_REG. (See Section 18. Low-
Voltage Inhibit (LVI).)
1 = LVI circuit for V_REG disabled
0 = LVI circuit for V_REG enabled
There is no LVI circuit for V_REGA.
LVI5OR3 — LVI Trip Point Voltage Select Bit for V_DD
LVI5OR3 selects the trip point voltage of the LVI circuit for V_DD.
(See Section 18. Low-Voltage Inhibit (LVI).)
1 = LVI trips at 3.3V
0 = LVI trips at 2.4V
URSTD — USB Reset Disable Bit
URSTD disables the USB reset signal generating an internal reset to
the CPU and internal registers. Instead, it will generate an interrupt
request to the CPU. (See Section 11. Universal Serial Bus Module
(USB).)
1 = USB reset generates a USB interrupt request to CPU
0 = USB reset generates a chip reset
LVID — LVI Disable Bit for V_DD
LVID disables the LVI circuit for V_DD. (See Section 18. Low-Voltage
Inhibit (LVI).)
1 = LVI circuit for V_DD disabled
0 = LVI circuit for V_DD enabled
Technical Data
72
Configuration Register (CONFIG)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor