MC908JB16DWE Datasheet, PDF (285/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt (IRQ)
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
An internal pullup resistor to V_DD is connected to IRQ pin; this can be
disabled by setting the IRQPD bit in the IRQ option control register
($001C).
15.6 PTE4/D– Pin
The PTE4 pin is configured as an interrupt input to trigger the IRQ
interrupt when the following conditions are satisfied:
• The USB module is disabled (USBEN = 0)
• PTE4 pin configured for external interrupt input (PTE4IE = 1)
Setting PTE4IE configures the PTE4 pin to an input pin with an internal
pullup device. The PTE4 interrupt is "ORed" with the IRQ input to trigger
the IRQ interrupt (see Figure 15-1 . IRQ Module Block Diagram).
Therefore, the IRQ status and control register affects both the IRQ pin
and the PTE4 pin. An interrupt on PTE4 also sets the PTE4 interrupt flag,
PTE4IF, in the IRQ option control register (IOCR).
15.7 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can
be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear the latches during the break
state. (See Section 8. System Integration Module (SIM).)
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
External Interrupt (IRQ)
Technical Data
285