MC908JB16DWE Datasheet, PDF (143/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
Addr.
Register Name
Bit 7
6
5
4
3
2
$0048
Timer 2 Channel 0 ^Read:
Register Low Write:
(T2CH0L) _Reset:
Timer 2 Channel 1 Status ^Read:
$0049
and Control Register Write:
(T2SC1) _Reset:
Bit 7
CH1F
0
0
6
5
4
3
2
Indeterminate after reset
CH1IE CH01IE MS1A ELS1B ELS1A
0
0
0
0
0
$004A
Timer 2 Channel 1 ^Read: _{Bit 15}
14
Register High Write:
(T2CH1H) _Reset:
13
12
11
10
Indeterminate after reset
Timer 2 Channel 1 ^Read: _{Bit 7}
6
$004B
Register Low Write:
(T2CH1L) _Reset:
5
4
3
2
Indeterminate after reset
= Unimplemented
Figure 10-2. TIM I/O Register Summary (Sheet 3 of 3)
1
Bit 0
1
Bit 0
TOV1 CH1MAX
0
0
9
Bit 8
1
Bit 0
10.5.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, PTE0/TCLK. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register (TSC) select the TIM clock source.
10.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Timer Interface Module (TIM)
Technical Data
143