MC908JB16DWE Datasheet, PDF (108/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
8.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register (CONFIG). If the SSREC bit is a logic 1, then the
stop recovery is reduced from the normal delay of 4096 OSCDCLK
cycles down to 2048 OSCDCLK cycles. This is ideal for applications
using canned oscillators that do not require long startup times from stop
mode. External crystal applications should use the full stop recovery
time, that is, with SSREC cleared in the configuration register (CONFIG).
8.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 8.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (See
8.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
8.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
8.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. Figure 8-8 flow charts the handling of
system interrupts.
Technical Data
108
System Integration Module (SIM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor