MC908GZ60CFUE Datasheet, PDF (94/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Configuration Register (CONFIG)
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module (see Chapter 11 Low-Voltage Inhibit
(LVI)). The voltage mode selected for the LVI should match the operating V_DD (see Chapter 21
Electrical Specifications) for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
NOTE
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE
Exiting stop mode by any reset will result in the long stop recovery.
The short stop recovery delay can be enabled when using a crystal or resonator and the
OSCENINSTOP bit is set. The short stop recovery delay can be enabled when an external oscillator
is used, regardless of the OSCENINSTOP setting.
The short stop recovery delay must be disabled when the OSCENINSTOP bit is clear and a crystal or
resonator is used.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 6 Computer Operating Properly (COP) Module.
1 = COP module disabled
0 = COP module enabled
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
94
Freescale Semiconductor