MC908GZ60CFUE Datasheet, PDF (175/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Port A
Table 13-2. Port A Pin Functions
PTAPUE
Bit
DDRA
Bit
PTA
Bit
I/O Pin
Mode
1
0
X⁽¹⁾
Input, V_DD(2)
0
0
X
Input, Hi-Z⁽⁴⁾
X
1
X
Output
1. X = Don’t care
2. I/O pin pulled up to V_DD by internal pullup device
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
Accesses to DDRA
Read/Write
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
Accesses to PTA
Read
Write
Pin
PTA7–PTA0⁽³⁾
Pin
PTA7–PTA0⁽³⁾
PTA7–PTA0
PTA7–PTA0
13.3.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the eight port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
NOTE
Pullup or pulldown resistors are automatically selected for keyboard
interrupt pins depending on the bit settings in the keyboard interrupt polarity
register (INTKBIPR) see 9.7.3 Keyboard Interrupt Polarity Register.
Address: $000D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 13-5. Port A Input Pullup Enable Register (PTAPUE)
PTAPUE7–PTAPUE0 — Port A Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port A pin configured to have internal pullup
0 = Corresponding port A pin has internal pullup disconnected
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
175