MC908GZ60CFUE Datasheet, PDF (218/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Enhanced Serial Communications Interface (ESCI) Module
ARUN— Arbiter Counter Running Flag
This read-only bit indicates the arbiter counter is running. Reset clears ARUN.
1 = Arbiter counter running
0 = Arbiter counter stopped
AROVFL— Arbiter Counter Overflow Bit
This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to
SCIACTL. Writing 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears
AROVFL.
1 = Arbiter counter overflow has occurred
0 = No arbiter counter overflow has occurred
ARD8— Arbiter Counter MSB
This read-only bit is the MSB of the 9-bit arbiter counter. Clear ARD8 by writing any value to SCIACTL.
Reset clears ARD8.
14.9.2 ESCI Arbiter Data Register
Address: $000B
Bit 7
Read: ARD7
Write:
Reset: 0
6
ARD6
5
ARD5
0
0
= Unimplemented
4
ARD4
0
3
ARD3
0
2
ARD2
0
1
ARD1
0
Figure 14-20. ESCI Arbiter Data Register (SCIADAT)
Bit 0
ARD0
0
ARD7–ARD0 — Arbiter Least Significant Counter Bits
These read-only bits are the eight LSBs of the 9-bit arbiter counter. Clear ARD7–ARD0 by writing any
value to SCIACTL. Writing 0s to AM1 and AM0 permanently resets the counter and keeps it in this idle
state. Reset clears ARD7–ARD0.
14.9.3 Bit Time Measurement
Two bit time measurement modes, described here, are available according to the state of ACLK.
1. ACLK = 0 — The counter is clocked with the bus clock divided by four. The counter is started when
a falling edge on the RxD pin is detected. The counter will be stopped on the next falling edge.
ARUN is set while the counter is running, AFIN is set on the second falling edge on RxD (for
instance, the counter is stopped). This mode is used to recover the received baud rate. See
Figure 14-21.
2. ACLK = 1 — The counter is clocked with one half of the ESCI input clock generated by the ESCI
prescaler. The counter is started when a 0 is detected on RxD (see Figure 14-22). A 0 on RxD on
enabling the bit time measurement with ACLK = 1 leads to immediate start of the counter (see
Figure 14-23). The counter will be stopped on the next rising edge of RxD. This mode is used to
measure the length of a received break.
14.9.4 Arbitration Mode
If AM[1:0] is set to 10, the arbiter module operates in arbitration mode. On every rising edge of SCI_TxD
(output of the ESCI module, internal chip signal), the counter is started. When the counter reaches $38
(ACLK = 0) or $08 (ACLK = 1), RxD is statically sensed. If in this case, RxD is sensed low (for example,
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
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Freescale Semiconductor