MC908GZ60CFUE Datasheet, PDF (184/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Input/Output (I/O) Ports
13.7.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a 1
to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$000C
Bit 7
0
0
6
5
0
DDRE5
0
0
= Unimplemented
4
DDRE4
0
3
DDRE3
0
2
DDRE2
0
1
DDRE1
0
Bit 0
DDRE0
0
Figure 13-18. Data Direction Register E (DDRE)
DDRE5–DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE5–DDRE0, configuring all port
E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 13-19 shows the port E I/O logic.
When bit DDREx is a 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a 0,
reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-6 summarizes the operation of the port E pins.
READ DDRE ($000C)
WRITE DDRE ($000C)
RESET
WRITE PTE ($0008)
DDREx
PTEx
PTEx
READ PTE ($0008)
Figure 13-19. Port E I/O Circuit
Table 13-6. Port E Pin Functions
DDRE
Bit
0
1
PTE
Bit
X⁽¹⁾
X
I/O Pin
Mode
Input, Hi-Z⁽²⁾
Output
Accesses to DDRE
Read/Write
DDRE5–DDRE0
DDRE5–DDRE0
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Accesses to PTE
Read
Write
Pin
PTE5–PTE0⁽³⁾
PTE5–PTE0
PTE5–PTE0
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
184
Freescale Semiconductor