MC908GZ60CFUE Datasheet, PDF (177/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Port B
DDRB7–DDRB0 — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB7–DDRB0, configuring all port
B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 13-8 shows the port B I/O logic.
When bit DDRBx is a 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-3 summarizes the operation of the port B pins.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRBx
PTBx
PTBx
READ PTB ($0001)
Figure 13-8. Port B I/O Circuit
Table 13-3. Port B Pin Functions
DDRB
Bit
0
1
PTB
Bit
X⁽¹⁾
X
I/O Pin
Mode
Input, Hi-Z⁽²⁾
Output
Accesses to DDRB
Read/Write
DDRB7–DDRB0
DDRB7–DDRB0
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Accesses to PTB
Read
Write
Pin
PTB7–PTB0⁽³⁾
PTB7–PTB0
PTB7–PTB0
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
177