MC908GZ60CFUE Datasheet, PDF (72/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Analog-to-Digital Converter (ADC)
3.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
R
Write:
Reset: 0
0
0
0
0
1
0
0
= Unimplemented
R
= Reserved
Figure 3-9. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Table 3-2. ADC Clock Divide Ratio
ADIV2
0
0
0
0
1
ADIV1
0
0
1
1
X⁽¹⁾
1. X = Don’t care
ADIV0
0
1
0
1
X⁽¹⁾
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source.
1 = Internal bus clock
0 = Oscillator output clock (CGMXCLK)
The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source
is not fast enough, the ADC will generate incorrect conversions. See 21.10 5.0-Volt ADC Characteristics.
f_ADIC =
f_CGMXCLK or bus frequency _{≅ 1 MHz}
ADIV[2:0]
MODE1 and MODE0 — Modes of Result Justification Bits
MODE1 and MODE0 select among four modes of operation. The manner in which the ADC conversion
results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns
right-justified mode.
00 = 8-bit truncation mode
01 = Right justified mode
10 = Left justified mode
11 = Left justified signed data mode
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
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Freescale Semiconductor