MC908GZ60CFUE Datasheet, PDF (255/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

I/O Registers
SPE SPMSTR
0
X⁽¹⁾⁾
1
0
1
1
1
1
1. X = Don’t care
Table 16-2. SPI Configuration
MODFEN
SPI Configuration
X
Not enabled
X
Slave
0
Master without MODF
1
Master with MODF
Function of SS Pin
General-purpose I/O;
SS ignored by SPI
Input-only to SPI
General-purpose I/O;
SS ignored by SPI
Input-only to SPI
16.12 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
16.12.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Address: $0010
Bit 7
6
5
4
3
2
1
Read:
SPRIE
Write:
R
SPMSTR CPOL CPHA SPWOM SPE
Reset: 0
0
1
0
1
0
0
R = Reserved
Figure 16-14. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
1 = Master mode
0 = Slave mode
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
255