MC908GZ60CFUE Datasheet, PDF (323/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Clock Generation Module (CGM) Characteristics
21.9.3 CGM Acquisition/Lock Time Information
Characteristic
Symbol
Min
Typ
Max
Unit
Acquisition mode entry frequency tolerance⁽¹⁾
Δ_ACQ
± 3.6
—
± 7.2
%
Tracking mode entry frequency tolerance⁽²⁾
Δ_TRK
0
—
± 3.6
%
LOCK entry frequency tolerance⁽³⁾
Δ_LOCK
0
—
± 0.9
%
LOCK exit frequency tolerance⁽⁴⁾
Δ_UNL
± 0.9
—
± 1.8
%
Reference cycles per acquisition mode period
n_ACQ
—
32
—
Reference cycles per tracking mode period
n_TRK
—
128
—
Automatic mode time to stable
t_ACQ
n_ACQ/f_{RCLK See note}⁽⁵⁾
—
s
Automatic stable to lock time
t_AL
n_TRK/f_{RCLK See note}⁽⁶⁾
—
s
Automatic lock time (t_ACQ + t_AL)⁽⁷⁾
t_LOCK
—
PLL jitter, deviation of average bus frequency
over 2 ms period
f_J
0
5
25
ms
f_RCLK x
—
0.025% x
Hz
N/4
1. Deviation between VCO frequency and desired frequency to enter PLL acquisition mode.
2. Deviation between VCO frequency and desired frequency to enter PLL tracking mode (stable).
3. Deviation between VCO frequency and desired frequency to enter locked mode.
4. Deviation between VCO frequency and desired frequency to exit locked mode.
5. Acquisition time is an integer multiple of reference cycles divided by reference clock.
6. Stable to lock time is an integer multiple of reference cycles divided by reference clock.
7. Maximum lock time depends on CGMXFC filter components, power supply filtering, and reference clock stability. PLL may
not lock if improper components or poor filtering and layout are used.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
323