MC908GZ60CFUE Datasheet, PDF (194/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Enhanced Serial Communications Interface (ESCI) Module
14.4.2 Transmitter
Figure 14-5 shows the structure of the SCI transmitter and the registers are summarized in Figure 14-4.
The baud rate clock source for the ESCI can be selected via the configuration bit, SCIBDSRC.
INTERNAL BUS
÷4
SCP1
SCP0
SCR2
SCR1
SCR0
PRE-
BAUD
SCALER DIVIDER
÷ 16
TXINV
ESCI DATA REGISTER
11-BIT
TRANSMIT
SHIFT REGISTER
H876543210L
SCI_TxD
CGMXCLK
OR
BUS CLOCK
PDS2
PDS1
PDS0
PSSB4
PSSB3
PSSB2
PSSB1
PSSB0
TRANSMITTER CPU
INTERRUPT REQUEST
M
PEN
PARITY
PTY
GENERATION
T8
TRANSMITTER
CONTROL LOGIC
SCTE
SCTE
SCTIE
TC
TCIE
SCTIE
TC
TCIE
Figure 14-5. ESCI Transmitter
SBK
LOOPS
ENSCI
TE
LINT
14.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control
register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control
register 3 (SCC3) is the ninth bit (bit 8).
14.4.2.2 Character Transmission
During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin. The ESCI
data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
194
Freescale Semiconductor