MC908GZ60CFUE Datasheet, PDF (169/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Chapter 13
Input/Output (I/O) Ports
13.1 Introduction
Bidirectional input-output (I/O) pins form seven parallel ports. All I/O pins are programmable as inputs or
outputs. All individual bits within port A, port C, port D and port F are software configurable with pullup
devices if configured as input port bits. The pullup devices are automatically and dynamically disabled
when a port bit is switched to output mode.
13.2 Unused Pin Termination
Input pins and I/O port pins that are not used in the application must be terminated. This prevents excess
current caused by floating inputs, and enhances immunity during noise or transient events. Termination
methods include:
1. Configuring unused pins as outputs and driving high or low;
2. Configuring unused pins as inputs and enabling internal pull-ups;
3. Configuring unused pins as inputs and using external pull-up or pull-down resistors.
Never connect unused pins directly to V_DD or V_SS.
Since some general-purpose I/O pins are not available on all packages, these pins must be terminated
as well. Either method 1 or 2 above are appropriate.
Addr.
$0000
$0001
$0002
$0003
Register Name
Port A Data Register ^Read:
(PTA) Write:
See page 173. _Reset:
Port B Data Register ^Read:
(PTB) Write:
See page 176. _Reset:
Port C Data Register ^Read:
(PTC) Write:
See page 178. _Reset:
Port D Data Register ^Read:
(PTD) Write:
See page 180. _Reset:
Bit 7
PTA7
PTB7
1
PTD7
6
PTA6
5
PTA5
PTB6
PTB5
PTC6
PTC5
PTD6
PTD5
= Unimplemented
4
3
PTA4
PTA3
Unaffected by reset
PTB4
PTB3
Unaffected by reset
PTC4
PTC3
Unaffected by reset
PTD4
PTD3
Unaffected by reset
2
PTA2
PTB2
PTC2
PTD2
Figure 13-1. I/O Port Register Summary (Sheet 1 of 3)
1
PTA1
PTB1
PTC1
PTD1
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
Bit 0
PTA0
PTB0
PTC0
PTD0
169