MC908GZ60CFUE Datasheet, PDF (152/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

MSCAN08 Controller (MSCAN08)
12.12.1 Message Buffer Outline
Figure 12-12 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 12-13. All bits of
the 13-byte data structure are undefined out of reset.
NOTE
The foreground receive buffer can be read anytime but cannot be written.
The transmit buffers can be read or written anytime.
Addr.
Register
Bit 7
6
5
4
3
2
1
Bit 0
$05b0
Read:
IDR0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
Write:
$05b1
Read:
IDR1
ID20
ID19
ID18 SRR (=1) IDE (=1)
ID17
ID16
ID15
Write:
$05b2
Read:
IDR2
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
Write:
$05b3
Read:
IDR3
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
Write:
$05b4
Read:
DSR0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write:
$05b5
Read:
DSR1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write:
$05b6
Read:
DSR2
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write:
$05b7
Read:
DSR3
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write:
$05b8
Read:
DSR4
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write:
$05b9
Read:
DSR5
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write:
$05bA
Read:
DSR6
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write:
$05bB
Read:
DSR7
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write:
$05bC
Read:
DLR
Write:
DLC3
DLC2
DLC1
DLC0
= Unimplemented
Figure 12-12. Receive/Transmit Message Buffer Extended Identifier (IDRn)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
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Freescale Semiconductor