MC908GZ60CFUE Datasheet, PDF (112/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

External Interrupt (IRQ)
RESET
ACK
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
CLR
D
Q
CK
SYNCHRONIZER
IMASK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
MODE
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 8-1. IRQ Module Block Diagram
When an interrupt pin is both falling-edge and low-level triggered (MODE = 1), the interrupt remains set
until both of these events occur:
• Vector fetch or software clear
• Return of the interrupt pin to a high level
The vector fetch or software clear may occur before or after the interrupt pin returns to a high level. As
long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR masks all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
Addr.
$001D
Register Name
Bit 7
6
5
4
3
IRQ Status and Control ^Read:
0
0
0
0
IRQF
Register (INTSCR) Write:
See page 114. _Reset:
0
0
0
0
0
= Unimplemented
Figure 8-2. IRQ I/O Register Summary
2
1
Bit 0
0
IMASK MODE
ACK
0
0
0
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
112
Freescale Semiconductor