MC908GZ60CFUE Datasheet, PDF (266/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Timer Interface Module (TIM1)
Addr.
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
Register Name
Bit 7
6
5
4
3
2
TIM1 Status and Control ^{Read: TOF}
TOIE TSTOP
0
0
PS2
Register (T1SC) Write: 0
TRST
See page 271. _Reset:
0
0
1
0
0
0
TIM1 Counter Register High
(T1CNTH)
See page 273.
Read:
Write:
Reset:
TIM1 Counter Register Low
(T1CNTL)
See page 273.
Read:
Write:
Reset:
TIM1 Counter Modulo Register
High (T1MODH)
See page 273.
Read:
Write:
Reset:
Bit 15
0
Bit 7
0
Bit 15
1
Bit 14
0
Bit 6
0
Bit 14
1
Bit 13
0
Bit 5
0
Bit 13
1
Bit 12
0
Bit 4
0
Bit 12
1
Bit 11
0
Bit 3
0
Bit 11
1
Bit 10
0
Bit 2
0
Bit 10
1
TIM1 Counter Modulo Register
Low (T1MODL)
See page 273.
Read:
Write:
Reset:
TIM1 Channel 0 Status and
Control Register (T1SC0)
See page 274.
Read:
Write:
Reset:
TIM1 Channel 0 Register High
(T1CH0H)
See page 277.
Read:
Write:
Reset:
Bit 7
1
CH0F
0
0
Bit 15
Bit 6
1
CH0IE
0
Bit 14
Bit 5
Bit 4
Bit 3
Bit 2
1
1
1
1
MS0B MS0A ELS0B ELS0A
0
0
0
0
Bit 13 Bit 12 Bit 11 Bit 10
Indeterminate after reset
TIM1 Channel 0 Register Low
(T1CH0L)
See page 277.
Read:
Write:
Reset:
TIM1 Channel 1 Status and
Control Register (T1SC1)
See page 274.
Read:
Write:
Reset:
TIM1 Channel 1 Register High
(T1CH1H)
See page 277.
Read:
Write:
Reset:
Bit 7
CH1F
0
0
Bit 15
Bit 6
CH1IE
0
Bit 14
Bit 5
Bit 4
Bit 3
Bit 2
Indeterminate after reset
0
MS1A ELS1B ELS1A
0
0
0
0
Bit 13 Bit 12 Bit 11 Bit 10
Indeterminate after reset
TIM1 Channel 1 Register Low ^Read: _{Bit 7}
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
(T1CH1L) Write:
See page 277. _Reset:
Indeterminate after reset
= Unimplemented
Figure 18-3. TIM1 I/O Register Summary
1
Bit 0
PS1
PS0
0
0
Bit 9
Bit 8
0
0
Bit 1
Bit 0
0
0
Bit 9
Bit 8
1
1
Bit 1
Bit 0
1
1
TOV0 CH0MAX
0
0
Bit 9
Bit 8
Bit 1
Bit 0
TOV1 CH1MAX
0
0
Bit 9
Bit 8
Bit 1
Bit 0
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
266
Freescale Semiconductor