MC908GZ60CFUE Datasheet, PDF (294/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Timer Interface Module (TIM2)
Address: $0033
Bit 7
Read: CH1F
Write: 0
Reset: 0
Address: $0456
Bit 7
Read: CH2F
Write: 0
Reset: 0
Address: $0459
Bit 7
Read: CH3F
Write: 0
Reset: 0
Address: $045C
Bit 7
Read: CH4F
Write: 0
Reset: 0
Address: $045F
Bit 7
Read: CH5F
Write: 0
Reset: 0
T2SC1
6
5
0
CH1IE
0
0
T2SC2
6
5
CH2IE MS2B
0
0
T2SC3
6
5
0
CH3IE
0
0
T2SC4
6
5
CH4IE MS4B
0
0
T2SC5
6
5
0
CH5IE
0
0
= Unimplemented
4
MS1A
0
4
MS2A
0
4
MS3A
0
4
MS4A
0
4
MS5A
0
3
ELS1B
0
2
ELS1A
0
3
ELS2B
0
2
ELS2A
0
3
ELS3B
0
2
ELS3A
0
3
ELS4B
0
2
ELS4A
0
3
ELS5B
0
2
ELS5A
0
1
TOV1
0
1
TOV2
0
1
TOV3
0
1
TOV4
0
1
TOV5
0
Figure 19-8. TIM2 Channel Status and Control Registers
(T2SC0:T2SC5) (Continued)
Bit 0
CH1MAX
0
Bit 0
CH2MAX
0
Bit 0
CH3MAX
0
Bit 0
CH4MAX
0
Bit 0
CH5MAX
0
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM2 counter registers matches the value in the TIM2 channel x registers.
When CHxIE = 1, clear CHxF by reading TIM2 channel x status and control register with CHxF set,
and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to
inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM2 CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
294
Freescale Semiconductor