MC908GZ60CFUE Datasheet, PDF (71/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

I/O Registers
3.8.2.3 Left Justified Signed Data Mode
In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only
difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two
LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single
channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All
subsequent results will be lost until the ADRH and ADRL reads are completed.
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Write:
Reset:
Unaffected by reset
Address: $003E
Read: AD1
AD0
0
0
0
0
0
0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 3-7. ADC Data Register High (ADRH) and Low (ADRL)
3.8.2.4 Eight Bit Truncation Mode
In 8-bit truncation mode, the ADRL register holds the eight MSBs of the 10-bit result. The ADRH register
is unused and reads as 0. The ADRL register is updated each time an ADC single channel conversion
completes. In 8-bit mode, the ADRL register contains no interlocking with ADRH.
Address: $003D
Bit 7
6
5
4
3
2
Read: 0
0
0
0
0
0
Write:
Reset:
Unaffected by reset
Address: $003E
Read: AD9
AD8
AD7
AD6
AD5
AD4
Write:
Reset:
Unaffected by reset
= Unimplemented
ADRH
1
Bit 0
0
0
ADRL
AD3
AD2
Figure 3-8. ADC Data Register High (ADRH) and Low (ADRL)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
71